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HP boffins have packed layers of RAM, caches and storage into a combined block of memristors and processor cores to create highly scalable "nanostore" systems. It's hoped these little monsters will chew through mountains of data with terrific energy efficiency.A memristor increases or decreases its electrical resistance depending on the direction of electrons flowing through it. Thus it is possible to store a binary bit in each memristor cell: if a low resistance indicates a '1', a high resistance indicates a '0'. Memristors are non-volatile, like flash, and can be accessed at near-DRAM speed.The nanostore design appears to place energy efficiency above data retrieval rates. HP Labs fellow Parthasarathy Ranganathan presented the blueprints at the San Jose Server Design Summit this week, according to EE Times.Ranganathan has a three to five year timescale in mind to develop the technology into a product. The chips will be ideal for crunching through huge datasets that have to be largely or fully in memory to be worked on in parallel. Plus, the nanometre-scale systems should be able to pack more storage capacity into data centres.He produced an IEEE paper in January 2011 titled From Microprocessors to Nanostores; Rethinking Data-Centric Systems [PDF] in which he discusses the nanostore concept in far more detail.
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Topic: From Microprocessors to Nanostores (Read 656 times)
